Infinitely stackable interconnect device and method
US7897503B2 · kind B2 · utility
63Cited by
15References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2006 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Aug 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical components may be placed within the via region in order to manipulate optical signals. Redistribution of electrical interconnection is accomplished on both top and bottom surfaces of the substrate of the interconnect chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.