High-voltage NMOS-transistor and associated production method

US7898030B2 · kind B2 · utility

Assignee

• austriamicrosystems AG

Inventors

• Martin Knaipp · Kufstein, AT
• Jong Mun Park · Graz, AT

Key dates

• Filing date: Aug 5, 2005
• Grant date: Mar 1, 2011
• Expiry date: Sep 20, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.