Analog duty cycle correction loop for clocks
US7898309B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | May 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Providing duty cycle correction can include determining whether a clock signal has a duty cycle greater than 50% based on averaging the clock signal and comparing that averaged clock signal to ½ VDD. When the duty cycle is greater than 50%, the clock signal can be selected. When the duty cycle is less than 50%, the inverted clock signal can be selected. Thus, a duty cycle corrected clock signal can be generated based on the clock signal or the inverted clock signal. Notably, a duty cycle control signal can be adjusted based on comparisons of an averaged, duty cycle corrected clock signal and predetermined low/high voltage ranges. Components performing comparing functions can be strobed based on a count performed on the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.