Phase doubler
US7898310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Apr 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1584
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A phase doubler driver circuit includes first control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to an input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to a difference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second ph…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.