Frequency-locked loop calibration of a phase-locked loop gain
US7898343B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Apr 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a calibrated phase-locked loop (PLL), which has a calibration mode for measuring a tuning gain of a variable frequency oscillator (VFO) and a PLL mode for normal operation. Calibration information based on the tuning gain is used during the PLL mode to regulate a PLL loop gain. During the calibration mode, the calibrated PLL operates as a frequency-locked loop (FLL) for low frequency lock times, and during the PLL mode the calibrated PLL operates as a PLL for high frequency accuracy and low noise. By regulating the PLL loop gain, the desired noise spectrum and dynamic behavior of the PLL may be maintained in spite of variations in the operating characteristics or in the characteristics of the PLL components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.