Methods and systems for calibrating a pipelined analog-to-digital converter
US7898452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2009 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Nov 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.