Logical design of graphics system with reduced shadowed state memory requirements
US7898546B1 · kind B1 · utility
3Cited by
28References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2006 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Aug 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing unit is designed to have validation logic utilizing a reduced memory space shadow memory as a source of state information for performing validation of commands. A semantic analysis is performed to generate the validation logic such that the reduced memory space shadow memory has a size small than a memory size required to store a full representation of a set of state variables associated with a class of commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.