Semiconductor memory device which includes memory cell having charge accumulation layer and control gate
US7898851B2 · kind B2 · utility
13Cited by
20References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Nov 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.