Memory structure for resolving addresses in a packet-based network switch
US7899052B1 · kind B1 · utility
60Cited by
24References
60Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/45
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Memory structure, and packet-based switch including the memory structure, having Address Resolution Table and Packet Data Buffer table employing a shared memory. Transmit Descriptor Table also may share memory. Address Resolution Table can be implemented with direct mapping, for which destination address key direct-mapped address search may be used. The memory structure and switch implement an IEEE Std. 802.3 communication protocol via multiple ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.