Interrupt processing in a layered virtualization architecture
US7900204B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 30, 2005 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45566
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of apparatuses, methods, and systems for processing interrupts in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a recognition logic, window logic, and evaluation logic. The event logic is to recognize an interrupt request. The window logic is to determine whether an interrupt window is open. The evaluation logic is to determine whether to transfer control to one of at least two virtual machine monitors in response to the interrupt request if the interrupt window is open.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.