ESD induced artifact reduction design for a thin film transistor image sensor array
US7902004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Nov 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
Abstract
A method is provided for fabricating an image sensor array in a manner that reduces the potential for defects resulting from electrostatic discharge events during fabrication of the image sensor array. The method includes: forming at least one pixel over a substrate, the pixel including a switching transistor and a photo-sensitive cell; and forming a dielectric interlayer over the pixel. A key step in the method of the present invention is depositing a first conductive layer over the dielectric interlayer. After the first conductive layer is formed, the image sensor array is well protected from ESD events because the first conductive layer spreads out any charge induced by tribo-electric charging events that may occur during subsequent fabrication processing steps, thereby reducing the potential for localized damage to the switching transistors upon the occurrence of ESD events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.