Low dropout regulator with stability compensation circuit
US7902801B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 4, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The present invention provides a low dropout (LDO) regulator with a stability compensation circuit. A “zero frequency” tracking as well as “non-dominant parasitic poles' frequency reshaping” are performed to achieve a good phase margin for the LDO by means of the compensation circuit. In this compensation method neither a large load capacitor nor its equivalent series resistance is needed to stabilize a regulator. LDO regulators, in system on chip application, having load capacitors in the range of few nano-Farads to few hundreds of nano-Farads can be efficiently compensated with this compensation method. A dominant pole for the regulator is realized at an internal node and the second pole at an output node of the regulator is tracked with a variable capacitor generated zero over a range of load current to cancel the effect of each other. A third pole of the system is pushed out above the unity gain frequency of the open loop transfer function with the help of the frequency compensation circuit. The compensation technique is very effective in realizing a low power, low-load-capacitor LDO desirable for system on chip applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.