High-bandwidth interconnect network for an integrated circuit
US7902862B2 · kind B2 · utility
7Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Dec 28, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.