Cascaded DAC architecture with pulse width modulation
US7903015B1 · kind B1 · utility
4Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Sep 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.