Comparator for a pipelined analog-to-digital converter and related signal sampling method
US7903017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Aug 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator for a pipelined ADC includes a sampling circuit coupled to a plurality of differential input voltages and a plurality of differential reference voltages, for sampling the plurality of differential input voltages according to a first clock signal and sampling the plurality of differential reference voltages according to a second clock signal, a preamplifier coupled to the sampling circuit comprising a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, for amplifying a voltage across the positive input terminal and the negative input terminal for generating a plurality of differential output voltages, and a latch circuit coupled to the preamplifier for latching the plurality of differential output voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.