Memory devices and methods for determining data of bit layers based on detected error bits
US7903459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Feb 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.