E/P durability by using a sub-range of a full programming range
US7903462B1 · kind B1 · utility
20Cited by
0References
21Claims
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Assignee
Inventors
Key dates
| Filing date | Sep 26, 2008 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.