Hardware arithmetic engine for lambda rule computations
US7904497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Aug 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0261
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114, 302). A three input adder (220, 228) sequentially sums the output of the second multiplier (214), inputs from the series of inputs, and the previous output of the engine (114, 302). A shift register (244) is used to feedback the output of the engine (114, 302) to the three input adder (220, 228) and second multiplier (214). A MUX (234) is used to route an initial value through the shift register (244) for the first cycle of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.