System for optimizing the performance and reliability of a storage controller cache offload circuit
US7904647B2 · kind B2 · utility
40Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2006 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Mar 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for offloading a cache memory is disclosed. The method generally includes the steps of (A) reading all of a plurality of cache lines from the cache memory in response to an assertion of a signal to offload of the cache memory, (B) generating a plurality of blocks by dividing the cache lines in accordance with a RAID configuration and (C) writing the blocks among a plurality of nonvolatile memories in the RAID configuration, wherein each of the nonvolatile memories has a write bandwidth less than a read bandwidth of the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.