Communication paths for enabling inter-sequencer communication following lock competition and accelerator registration
US7904696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jul 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.