Multi-thread power-gating control design
US7904736B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jan 4, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.