Patent · US Active

Pipelined cyclic redundancy check for high bandwidth interfaces

US7904787B2 · kind B2 · utility

3Cited by

4References

11Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Scott Douglas Clark · Rochester, US
Dorothy Marie Thelen · Rochester, US

Key dates

Filing date	Jan 9, 2007
Grant date	Mar 8, 2011
Priority date	—
Expiry date	Jan 7, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH04L1/0052
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.