System and method for runtime placement and routing of a processing array
US7904848B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 13, 2007 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Jan 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processing units disposed on a layer permitting interconnection between connection nodes; and a mapping unit adapted to substantially simultaneously optimize placement of the tasks on the plurality of programmable processing units and routing of interconnections between the plurality of processing units, the mapping unit adapted to select one placement algorithm among a plurality of predetermined placement algorithms and to select one routing algorithm from a plurality of predetermined placement algorithms, the selection configured to prefer use of non-random algorithms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.