Hardware emulator having a selectable write-back processor unit
US7908465B1 · kind B1 · utility
3Cited by
3References
20Claims
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Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Apr 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for emulating a hardware design comprising an instruction execution unit for executing at least one instruction, a memory for providing data to the instruction execution unit for processing into an output bit, and a write enable logic for controlling writing the output bit from the instruction execution unit to the memory. In this manner, the output bit produced by the instruction execution unit executing an instruction may be selectably stored in memory to facilitate efficient processing of conditional emulation operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.