Semiconductor integrated circuit comprising master-slave flip-flop and combinational circuit with pseudo-power supply lines
US7908499B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2007 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Jan 12, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device using a ZSCCMOS circuit, a combinational circuit includes a plurality of logic gate circuits, and receives an output of a data holding circuit. The data holding circuit can continue to hold data during cut-off of power supply, and when receiving a predetermined value as a control signal, outputs a predetermined fixed value. A logic gate circuit which outputs “L” when the output of the data holding circuit has the predetermined fixed value has power supply ends connected to a pseudo-power supply line VDDV and a low potential power supply line VSS. A logic gate circuit which outputs “H” when the output of the data holding circuit has the predetermined fixed value has power supply ends connected to a high potential power supply line VDD and a pseudo-power supply line VSSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.