Failure prediction circuit and method, and semiconductor integrated circuit
US7908538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2007 |
| Grant date | Mar 15, 2011 |
| Priority date | — |
| Expiry date | Mar 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.