Method of fabricating array substrate
US7910414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2009 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Nov 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.