Interfacing at low temperature using CMOS technology
US7911265B2 · kind B2 · utility
8Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2008 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Apr 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention concerns interfacing to electronic circuits or systems operating at low temperature or ultra-low temperature using complementary metal-oxide semiconductor (CMOS) technology. Low temperature in this case refers to cryogenic temperatures in particular, but not exclusively, to the 4.2 K region. Ultra-low temperatures here refers to the sub-1 K range, usually accessed using dilution refrigerator systems. The electronic circuits comprise a controller (for writing and manipulation), an observer (for readout and measurement) circuits, or both, fabricated from ultra-thin silicon-on-insulator (SOI) CMOS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.