Semiconductor memory device and method of testing semiconductor memory device
US7911861B2 · kind B2 · utility
3Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2008 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a memory that stores data, an input/output unit and a loopback circuit. The input/output unit inputs and outputs data of a predetermined number of bits in synchronization with a clock signal. The input/output unit may include, but is not limited to, the same number of data input/output terminals as the predetermined number of bits. The loopback circuit performs loopback operation to read data of the predetermined number of bits out of a first optional area of the memory and to write the data into a second optional area of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.