Prognosis of faults in electronic circuits
US7912669B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.