Method of testing data paths in an electronic circuit
US7913129B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2008 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jun 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing an electronic circuit having a plurality of data transfer operators operating on memory resources defining a shared memory space is described. According to at least one embodiment, the shared memory space is initialized by writing data items to the shared memory space, and each data item is unique in the shared memory space. All or some of the shared memory space is partitioned into a plurality of disjoint memory blocks, the memory blocks being organized into one or more groups of blocks, each memory block belongs to one of the groups, and all memory blocks of the same group have the same size. A test scenario comprising at least one data transfer operation is executed, and the content of the shared memory space is verified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.