Structure for a duty cycle correction circuit
US7913199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2008 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00221
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.