Wafer level sensing package and manufacturing process thereof
US7915065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Dec 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.