Double patterning techniques and structures
US7915171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | May 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3088
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.