Patent · US Active

Method and algorithm of high precision on-chip global biasing using integrated resistor calibration circuits

US7915950B2 · kind B2 · utility

2Cited by
8References
18Claims
0Family size

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Key dates

Filing dateJun 20, 2008
Grant dateMar 29, 2011
Priority date—
Expiry dateJun 20, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG05F3/08
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

Systems and methods for providing bias currents to multiple analog circuits are disclosed. An integrated circuit comprises a calibration circuit which compares a high tolerance external component to a plurality of internal components manufactured to span the variability of the process, voltage and temperature. The best fitting internal component is communicated to bias circuits which can select an internal component from a local plurality of internal components with matching desired characteristics. In this manner, analog circuits can be locally biased with the tolerance usually associated with a high tolerance external reference component, without the necessity for a local external reference component.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.