Creation of capacitors equipped with means to reduce the stresses in the metal material of their lower structures
US7916449B2 · kind B2 · utility
1Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Jun 6, 2008 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jul 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.