Circuit providing load isolation and memory domain translation for memory module
US7916574B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2010 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Nov 29, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.