Apparatus and method for controlling hybrid ARQ memory in broadband wireless access communication system
US7916719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jan 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1845
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and HARQ memory apparatus in a BWA communication system are provided where the HARQ memory apparatus includes a memory configured to partition the entire memory area in units of slots corresponding to the size of a concatenation block, to input/output a plurality of channel data to the slot in units of the concatenation block, to store a new concatenation block in an empty slot, and to combine a retransmitted concatenation block with a prestored concatenation block and store the combined concatenation block at a prestored location. Accordingly, the required amount of memory can be reduced by using a buffer efficiently. In particular, when a memory is embedded in an integrated circuit, the size and power consumption of the integrated circuit can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.