Adaptive equalizer for use with clock and data recovery circuit of serial communication link
US7916780B2 · kind B2 · utility
17Cited by
1References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jul 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03598
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.