Systems and arrangements for clock and data recovery in communications
US7916820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2006 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Feb 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.