Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit
US7916822B2 · kind B2 · utility
6Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Jul 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.