Performance based packet ordering in a PCI express bus
US7917680B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2005 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Nov 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.