Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation
US7917701B2 · kind B2 · utility
8Cited by
7References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 12, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.