Memory protection for embedded controllers
US7917716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Dec 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for protecting data in a system including a main processor, an embedded controller, and a memory. In response to a power-on-reset (POR), access to the memory is enabled, e.g., access by the embedded controller. First data is read from the memory (e.g., by the embedded controller) in response to the enabling, where the first data are usable to perform security operations for the system prior to boot-up of the main processor. The first data are used, e.g., by the embedded controller, to perform one or more security operations for the system, then access to the memory, e.g., by the embedded controller, is disabled, where after the disabling the memory is not accessible, e.g., until the next POR initiates enablement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.