Data processing architectures for packet handling using a SIMD array
US7917727B2 · kind B2 · utility
5Cited by
28References
18Claims
0Family size
Assignee
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Key dates
| Filing date | May 23, 2007 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Sep 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.