Resetting of multiple processors in an electronic device
US7917812B2 · kind B2 · utility
5Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2006 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Automatic resetting of a group of multiple processors in an electronic device wherein the processors are arranged in either a cascade chain or master-slave configuration. Upon the receipt of an originating reset signal by any one of the multiple processors the remaining processors are reset upon receipt of a forced reset signal generated by one of the processors in the group. The system states prior to the originating reset of each processor is refreshed to ensure compatible synchronization of system states and thus proper communication among the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.