Thin film transistors with poly(arylene ether) polymers as gate dielectrics and passivation layers
US7919825B2 · kind B2 · utility
4Cited by
9References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2007 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Jun 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/471
- WIPO fieldMacromolecular chemistry, polymers
- WIPO sectorChemistry
Abstract
The use of a poly(arylene ether) polymer as a passivation or gate dielectric layer in thin film transistors. This poly(arylene ether) polymer includes polymer repeat units of the following structure:—(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n—where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1−m, and at least one of the aryl radicals is grafted to the backbone of the polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.