Resistance change nonvolatile memory device
US7920408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2008 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Aug 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.