Apparatus and method for secure hash algorithm
US7921300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2004 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Sep 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the hash operation. The single, atomic hash instruction has an opcode field and a repeat prefix field. The opcode field prescribes that the x86-compatible microprocessor accomplish the hash operation. The repeat prefix field is coupled to the opcode field and indicates that the hash operation prescribed by the single, atomic hash instruction is to be accomplished on one or more message blocks. The x86-compatible microprocessor has a hash unit that is configured to execute a plurality of hash computations on each of the one or more message blocks to generate a corresponding intermediate hash value, where a last intermediate hash value that is computed for a last message block after processing all previous message blocks includes a message digest corresponding to the one or more message blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.