Method and apparatus for synchronizing central processing units in a multiprocessor apparatus
US7921317B2 · kind B2 · utility
4Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2008 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Oct 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.